Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
نویسندگان
چکیده
منابع مشابه
Blue Visions Technologies Vlsi Bv001vlsi14 Design Flow for Flip-flop Grouping in Data-driven Clock Gating
Clock gating is a predominant technique used for power saving. It is observed that the commonly used synthesis-based gating still leaves a large amount of redundant clock pulses. Data-driven gating aims to disable these. To reduce the hardware overhead involved, flip-flops (FFs) are grouped so that they share a common clock enabling signal. The question of what is the group size maximizing the ...
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Data-driven clock gating is reducing the total power consumption of VLSI chips by 20%. There, flip-flops are grouped and share a common clock signal. Finding the optimal clusters is the key for maximizing the power savings. Clustering by the minimal cost perfect graph matching algorithm (MCPM) proposed by other works is not optimal. We show that the optimal clustering problem is NP-hard, and st...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2014
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2013.2253338